Files
fpga/digikey tutorials/part 3/and_gate.v
2023-01-28 22:21:48 -05:00

21 lines
493 B
Verilog

// module: button 0 lights up 2 leds, button 0 and 1 light up another
module and_gate (
// Inputs
input [1:0] pmod,
// Outputs
output [3:0] led
);
// Wire (net) declarations (internal to module)
wire not_pmod_0;
// Continous assignmen:replicate 1 wire to 2 outputs
assign not_pmod_0 = ~pmod[0];
assign led[1:0] = {2{not_pmod_0}};
// Continuous assignment: NOT and AND operators
assign led[2] = not_pmod_0 & ~pmod[1];
endmodule